As the density of integrated circuits has increased, there has been a need to reduce the size of associated capacitors in, for example, Dynamic Random Access Memories (DRAMs). However, there may also be a need to increase the per unit area capacitance of such capacitors, which may be difficult given that the overall size of the capacitors may be reduced for use in highly integrated circuits. One type of capacitor developed to address the above issues in the Metal-Insulator-Metal (MIM) type capacitor.
FIGS. 1-3 are cross sectional views illustrating a conventional method of fabricating a MIM capacitor. In particular, FIG. 1 shows a chip region (C) and a scribe region (S) of an integrated circuit substrate. According to FIG. 1, an interlayer dielectric (ILD) layer 3 is formed on the integrated circuit substrate in the chip and scribe regions. The ILD layer 3 includes a lower metal layer 5a in the chip region and a metal layer 5b in the scribe region. The lower metal layer 5a in the chip region can provide a lower electrode of the MIM capacitor, whereas the metal layer 5b in the scribe region can provide a first alignment key (K1). The lower metal layer 5a and the metal layer 5b can include copper.
A dielectric layer 7 is formed on the ILD layer 3 including on the lower metal layer 5a and on the metal layer 5b. A photo-resist material is formed on the dielectric layer 7 and patterned to provide a first photo-resist pattern 9 on the dielectric layer 7 including an opening 9k therein.
According to FIG. 2, a portion of the ILD layer 3 in the scribe region is etched using the first photo-resist pattern 9 to form a second alignment key (K2) in the scribe region. As further shown in FIG. 2, an upper metal layer 11 and a hard mask layer 13 are formed on the dielectric layer 7 and conformally in the second alignment key K2. A second photo-resist material is formed on the hard mask layer 13 and is patterned to provide a second photo-resist pattern 15.
According to FIG. 3, the second photo-resist pattern 15 is used to remove portions of the hard mask layer 13 and the upper metal layer 11 that are outside (i.e., not beneath) the second photo-resist pattern 15, thereby forming an upper metal electrode 11a and hard mask pattern 13a thereon to provide the MIM type capacitor structure as shown in FIG. 3.
MIM type capacitors are also discussed in, for example, U.S. Pat. No. 5,926,359, U.S. Pat. No. 6,180,976, and Korean patent application no. KR 2004-86682.